The supply current drawn by a microprocessor, such as may be used in notebook, desktop, and system server. applications, typically varies over a relatively wide range and depends upon its activity level. For example, when the clock to the microprocessor is turned on, a substantial capacitive charging and discharging current is drawn; on the other hand, when the clock is turned off, only a leakage is drawn. Now even though there is in fact a leakage current, the power supply specifications of manufacturers of microprocessors often assume zero leakage current, and a prescribed maximum current (e.g., on the order of 100 amps). Moreover, microprocessor manufacturers recognize that as the current switches between relatively low and relatively high current values, the voltage regulator produces a transient on its output voltage.
This transient effect is shown in the timing diagrams of FIGS. 1 and 2. In particular, FIG. 1 shows a relatively large increase (large or full load demand) in current I at a time t0 and a relatively large current decrease (negligible or no load demand) at time t1. FIG. 2 shows a ‘droop’ 21 in the output voltage of the regulator that is associated with (and having an undershoot that slightly lags) the increase in current at time t0, and an overshoot in the recovery of the output voltage to its no load condition 22 that is associated with (and slightly lags) the decrease and return to a no load condition in current at time t1. The droop differential must fall within the safe operating range of the microprocessor. The droop level 21 of the output voltage is a data integrity limit below which data can expected to be lost, while the upper level 22 of the output voltage is a reliability limit that serves to avoid stressing the gates of the microprocessor.
In an effort to deal with these limits, rather than specifying that the voltage regulator must deliver a constant output voltage, microprocessor manufacturers specify a load line wherein the regulated voltage decreases linearly with increase in current, which allows the regulated voltage to vary during normal operation. This is graphically shown in FIG. 3, which depicts a nominal load line 31 midway between an upper load line specification limit 31U and a lower load line specification limit 31L.
Now although a load line specification is acceptable where the leakage current is in the vicinity of zero amps, it becomes problematic as the leakage current increases, as it effectively ‘squeezes’ the output voltage range over which the converter may regulate. This leakage current issue becomes especially non-trivial as semiconductor manufacturers continue to reduce line widths and thickness of gate oxides of the integrated circuits they produce, which have lead to body leakage and tunneling across the gate oxide.
Indeed, as graphically shown at 33 in FIG. 3, the leakage component of the output current can be on the order of 30%–40%, or greater, of the total current. This effectively means that when the current transitions from a no load condition to a full load condition, as described above with reference to FIG. 1, the current actually transitions from a substantial leakage current value to a full load current value, as shown at 34 in FIG. 3. The associated voltage transient response resulting from the load line is shown at 35 as transitioning between a leakage voltage value VLEAK, which is less that the value it would have at zero leakage current, and a full load voltage value VFULL LOAD, the latter being less than the leakage voltage value by the differential voltage VDROOP, as shown.
In addition to being a non-negligible parameter, the leakage current is highly variable among manufactured part populations and may have a range of variation as large as three or four to one.